1. Field of the Invention
The present invention relates to an AD converter and an AD conversion method to convert an analog signal such as a voltage to a digital signal, and more particularly, to a correction processing.
2. Description of Related Art
With recent advancement of computer systems, high-speed operation and high accuracy are required in AD converters. One of AD conversion methods includes parallel (flash) processing, where an input analog signal is compared with a reference voltage at one time with multiple comparators arranged in parallel. This parallel processing is suitable for high-speed processing. In order to accomplish high accuracy (high-resolution ability) with this parallel processing, the number of comparators or resistance elements of a ladder circuit generating a reference voltage is increased, for example. This method, however, increases size of the circuit.
Other AD conversion methods include sequential comparison processing, where an input analog signal and a reference voltage are repeatedly compared by one comparator. According to this processing, it is possible to accomplish high accuracy with a simple circuit configuration by increasing the number of times of comparison. However, as the number of times of comparison is increased, high-speed operation cannot be achieved.
As stated above, each of the parallel processing and the sequential comparison processing has advantages and disadvantages. A related art (Japanese Unexamined Patent Application Publication No. 5-335953) is disclosed for realizing high-speed operation and high accuracy of the AD conversion processing in consideration of these advantages and disadvantages. This related art generates upper eight bits of the digital signal by parallel processing where high-speed operation is possible, and generates lower two bits to correct the error of the least significant bit of this upper eight bits by sequential comparison processing that uses fewer elements.
However, according to the technique disclosed in the above-described Japanese Unexamined Patent Application Publication No. 5-335953, when the sequential comparison processing is carried out, reconversion is performed using a signal having a least significant bit of “1” regardless of the value of the least significant bit of the upper eight bits. As such, it is impossible to correct the error when the upper bit is carried up or moved down due to the error of the least significant bit.